EDN

Wafer Level Chip Size Package

This application note provides guidelines for the use of Wafer Level Chip Size Packages (WLCSP). The information in this application note can be used throughout the various stages of WLCSP use. This ...
Nasdaq

Akoustis Completes Wafer Level Package Demonstrator and Ships Sample to Tier-1 Mobile Device OEM

Las Vegas, NV, Jan. 09, 2020 (GLOBE NEWSWIRE) -- Akoustis Technologies, Inc. (NASDAQ: AKTS) (“Akoustis” or the “Company”), an integrated device manufacturer (IDM) of patented bulk acoustic wave (BAW) ...

Aehr Receives $14 Million Order from Lead AI Processor Customer for Multiple New Fully Automated FOX-XP Wafer Level Burn-In Systems

FREMONT, CA / ACCESS Newswire / February 26, 2026 / Aehr Test Systems (NASDAQ:AEHR), a leading provider of test and burn-in solutions for semiconductor devices used in artificial intelligence (AI), ...
EDN

Reportlinker Adds Embedded Wafer-Level-Packages: Fan-out WLP / Chip Embedding in Substrate

Historically, embedded IC package technology is not new at all: several players such as Freescale with its RCP, Infineon with its eWLB and Ibiden for die embedding into PCB laminated substrates have ...
Nasdaq

Akoustis Locks Process Flow for First Wafer-Level-Chip-Scale Package (WLCSP) for XBAW Filters

Charlotte, N.C., Feb. 01, 2021 (GLOBE NEWSWIRE) -- Akoustis Technologies, Inc. (NASDAQ: AKTS) (“Akoustis” or the “Company”), an integrated device manufacturer (IDM) of patented bulk acoustic wave (BAW ...
Seeking Alpha

Aehr Seeing Momentum in Package-Level Burn-In Alongside Expanding Wafer-Level Burn-in Demand

FREMONT, CA / ACCESS Newswire / November 12, 2025 / Aehr Test Systems (AEHR), a worldwide supplier of semiconductor test and burn-in solutions, today announced the shipment of its Dual-Echo™ test and ...
Electronic Design

Wafer-Level Chip-Scale Package Favors Small-Form-Factor ASICs

A fully qualified, high-performance, low-power and small-form-factor wafer-level chip-scale package (W-CSP) developed by Oki Semiconductor satisfies a wide range of ASIC design demands. Targeting chip ...
Semiconductor Engineering

Fan-Out Wafer Level eWLB Technology As An Advanced System-in-Package Solution

A look at design considerations for a double-sided RDL, including board-level reliability and the challenges of higher density. System-in-Package (SiP) technology continues to be essential for higher ...
Houston Chronicle

(BW) Wafer-Level Packaging Requirements Boost Orders for Jordan Valley Semiconductors' Advanced X-ray Metrology Systems

Semiconductor metrology equipment manufacturer Jordan Valley Semiconductors announced that they have sold, installed and qualified multiple units of their JVX 6200 system to leading memory ...
Semiconductor Engineering

Easing The Stress For Package-Level Burn-In

Considered something of a necessary evil, burn-in of IC packages during production does a great job of weeding out latent defects so they don’t turn into failures in the field. But as AI and ...
Business Insider

Akoustis Completes Wafer Level Package Demonstrator and Ships Sample to Tier-1 Mobile Device OEM

– WLP Package Footprint Enables Form Factor Suitable for 5G Mobile Device Market – – Qualified WLP Packaging Expected in the Second Half of CY20 – Las Vegas, NV, Jan. 09, 2020 (GLOBE NEWSWIRE) -- ...