Terry Hook of IBM recently contributed an article to ASN about FinFET isolation issues on bulk vs. SOI. It generated immense interest, and created lots of discussion on various LinkedIn groups. In ...

Researchers unveil a roadmap for 2D transistor gate stack design, marking a key step toward ultra-efficient chips that could replace silicon technology. For decades, silicon-based CMOS technology has ...

Artificial intelligence (AI) has become the workload that defines today’s semiconductor scaling. Whether in hyperscale data centers training foundation models or at the network edge executing ...

BEAVERTON, Ore. — Intel Labs says it has successfully fabricated an indium-gallium-arsenide field-effect transistor (FET) atop a silicon substrate by integrating a high-k gate stack. As in Intel's ...

For more than three decades bulk-silicon MOSFET has been the transistor workhorse of CMOS technology. We have become terribly addicted to the density and performance gain from shrinking it. More speed ...

Integrating 2D materials into conventional semiconductor manufacturing processes may be one of the more radical changes in the chip industry’s history. While there is pain and suffering associated ...